In the case that a clock signal of a SDH (Synchronous Digital Hierarchy) signal or an Ethernet (registered trademark) signal is extracted from an OTN (Optical Transport Network) signal, a high frequency jitter component and a low frequency wander component are caused by the asynchronous stuff multiplex method.
There are four problems, which will be mentioned later, in the case of suppressing the high frequency jitter and the low frequency wander.
FIG. 1 is a diagram for explaining a first problem which is caused in a PLL (Phase Locked Loop) circuit related to the present invention. The first problem is that jitter/wander (Waiting Time Jitter/Wander) is caused at a time of zero stuff as a fate of the asynchronous stuff multiplex method as shown in FIG. 1.
In FIGS. 1 to 4, OTU (Optical Transport Unit) 3 is an optical interface with a rate of about 40 Gb/s which is specified in OTN. STM (Synchronous Transport Module)-64 and 10 GbE (Gigabit Ethernet) are interfaces with a rate of about 10 Gb/s which are specified by SDH and Ethernet respectively.
According to the stuff multiplex method, it is possible originally to calculate the optimum PLL cut-off frequency through monitoring frequency of the OTN signal, and the SDH signal or the Ethernet signal. However, a high precision oscillator (oven-controlled crystal oscillator) or an external synchronization clock (high precision clock provided by so-called Building Integrated Timing Supply, Synchronization Supply Unit or Clock Supply Module) is necessary for monitoring the frequency. For this reason, system becomes very expensive.
IF the PLL cut-off frequency is made low in order to suppress the jitter/wander at the time of zero stuff, the frequency tracking ability of the PLL circuit declines. In this case, an output wander of the PLL circuit increases.
FIG. 2 is a diagram for explaining a second problem which is caused in the PLL circuit related to the present invention. The second problem is that a link failure may be caused in some cases due to a memory slip of a regenerated signal.
As shown in FIG. 2, a memory for adjusting frequency (memory for switching clock signal) is used in the case of regenerating the SDH signal or the Ethernet signal from the OTN signal. However, if the SDH signal or the Ethernet signal does not follow the OTN signal continuously, the memory slip of the regenerated signal due to memory overflow or memory underflow is caused. As a result, the link failure may be caused finally.
In this case, the second problem may be solved through making a frequency tracking speed high, but jitter/wander suppressing performance is lost instead.
FIG. 3 is a diagram for explaining a third problem which is caused in the PLL circuit related to the present invention. The third problem is that in the case that the SDH signal or the Ethernet signal is transferred through a multistage connection (cascade connection or tandem connection) as shown in FIG. 3, the wander is accumulated, and consequently the memory slip of the regenerated SDH signal or the regenerated Ethernet signal may be caused in some cases.
The wander caused by the multistage connection, which is different from the wander due to the stuff multiplex method described in the first problem, strongly depends on both of a jitter/wander component of PLL and a network wander component.
However, it is necessary to carry out calculation by use of all combinations of a large number of parameters in order to simulate the jitter/wander component of PLL itself and the jitter/wander component of the network wander.
Therefore, it is very difficult to calculate the wander due to the multistage connection beforehand.
FIG. 4 is a diagram for explaining a fourth problem which is caused in the PLL circuit related to the present invention. The fourth problem is that, in the case that a system which has been failed is restored, an output frequency of the restored system becomes abnormal, and consequently output frequencies of all other systems, which are latter part of the multistage connection, may become abnormal one after another with a delay in some cases. As shown in FIG. 4, the fourth problem may be caused in a configuration, similarly to the configuration described in FIG. 3, in which the SDH signal or the Ethernet signal is transferred through the multistage connection. Similarly to the second problem, the fourth problem may be solved through making the frequency tracking speed high, but the jitter/wander suppressing performance is lost instead.
Accordingly, it is necessary to develop a system which can realize the high-speed frequency tracking performance while satisfying the jitter/wander suppressing performance.
As a document related to the present invention, there is a document which discloses an art that only Transient Wander component (jump component of input phase) is detected automatically, and an output phase is adjusted to an input phase preceding the jump (for example, refer to patent document 1).
Moreover, there is another document disclosing an art which can make a phase error small and can suppress the high frequency jitter component and the low frequency wander component simultaneously (for example, refer to patent document 2).